Architecture-specific

Architecture information structure Contains comprehensive information about the detected CPU architecture, including architecture type, byte order, and capability information. This structure provides a unified view of the system's architectural characteristics and includes convenient methods for common architectural queries.

Key Information

• Architecture Type: Specific CPU architecture family and variant
• Byte Order: System endianness (little/big endian)
• Pointer Size: Address space size (32-bit vs 64-bit)
• Cache Line Size: Typical cache line size for alignment optimization
• Architecture Name: Human-readable architecture identifier

Performance Implications

• Cache Line Alignment: Use cache_line_size for optimal memory layout
• SIMD Support: Check hasSimdSupport() for vectorization opportunities

• Unaligned Access: Use supportsUnalignedAccess() for memory access patterns

  optimization

  constexpr auto arch_info = trlc::platform::getArchitectureInfo();
   
  // Optimize based on architecture capabilities
  if constexpr (arch_info.hasSimdSupport()) {
      // Use SIMD instructions
      processWithSimd(data);
  } else {
      // Use scalar fallback
      processScalar(data);
  }
   
  // Align data to cache line boundary
  alignas(arch_info.cache_line_size) char buffer[1024];

Note

All member functions are constexpr and evaluate at compile time

See also

getCpuArchitecture() for simple architecture detection

getArchitectureInfo() for creating instances of this structure

Since

1.0.0