architecture.hpp

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#pragma once
 
#include <cstddef>  // For size_t
 
#include "endianness.hpp"  // For ByteOrder enum and endianness functions
 
namespace trlc {
namespace platform {
 
enum class CpuArchitecture : int {
    unknown = 0,  
    x86,          
    x86_64,       
    arm_v6,       
    arm_v7,       
    arm_v8_32,    
    arm_v8_64,    
    mips,         
    mips_64,      
    powerpc,      
    powerpc_64,   
    risc_v_32,    
    risc_v_64,    
    sparc,        
    sparc_64      
};
 
struct ArchitectureInfo {
    CpuArchitecture architecture;  
    ByteOrder byte_order;          
    int pointer_size_bits;         
    size_t cache_line_size;        
    const char* arch_name;         
 
    constexpr bool is64Bit() const noexcept { return pointer_size_bits == 64; }
 
    constexpr bool is32Bit() const noexcept { return pointer_size_bits == 32; }
 
    constexpr bool isLittleEndian() const noexcept {
        return byte_order == ByteOrder::little_endian;
    }
 
    constexpr bool supportsUnalignedAccess() const noexcept {
        // x86/x64 and most modern ARM cores support unaligned access efficiently
        return architecture == CpuArchitecture::x86 || architecture == CpuArchitecture::x86_64 ||
               architecture == CpuArchitecture::arm_v7 ||
               architecture == CpuArchitecture::arm_v8_32 ||
               architecture == CpuArchitecture::arm_v8_64;
    }
 
    constexpr bool hasSimdSupport() const noexcept {
        return architecture == CpuArchitecture::x86 || architecture == CpuArchitecture::x86_64 ||
               architecture == CpuArchitecture::arm_v7 ||
               architecture == CpuArchitecture::arm_v8_32 ||
               architecture == CpuArchitecture::arm_v8_64;
    }
 
    constexpr bool isARM() const noexcept {
        return architecture == CpuArchitecture::arm_v6 || architecture == CpuArchitecture::arm_v7 ||
               architecture == CpuArchitecture::arm_v8_32 ||
               architecture == CpuArchitecture::arm_v8_64;
    }
 
    constexpr bool isX86() const noexcept {
        return architecture == CpuArchitecture::x86 || architecture == CpuArchitecture::x86_64;
    }
};
 
namespace detail {
 
constexpr CpuArchitecture detectCpuArchitecture() noexcept {
// x86/x64 detection
#if defined(__x86_64__) || defined(__x86_64) || defined(__amd64__) || defined(__amd64) || \
    defined(_M_X64)
    return CpuArchitecture::x86_64;
#elif defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i586__) || \
    defined(__i686__) || defined(_M_IX86)
    return CpuArchitecture::x86;
 
// ARM detection
#elif defined(__aarch64__) || defined(_M_ARM64)
    return CpuArchitecture::arm_v8_64;
#elif defined(__arm__) || defined(_M_ARM)
    #if defined(__ARM_ARCH_8__) || defined(__ARM_ARCH_8A__)
    return CpuArchitecture::arm_v8_32;
    #elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || \
        defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__)
    return CpuArchitecture::arm_v7;
    #elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || \
        defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__)
    return CpuArchitecture::arm_v6;
    #else
    return CpuArchitecture::arm_v7;  // Default to v7 for unknown ARM
    #endif
 
// MIPS detection
#elif defined(__mips__) || defined(__mips) || defined(__MIPS__)
    #if defined(__mips64__) || defined(__mips64) || (_MIPS_SIM == _ABI64)
    return CpuArchitecture::mips_64;
    #else
    return CpuArchitecture::mips;
    #endif
 
// PowerPC detection
#elif defined(__powerpc__) || defined(__powerpc) || defined(__ppc__) || defined(__ppc) || \
    defined(_M_PPC)
    #if defined(__powerpc64__) || defined(__ppc64__) || defined(__PPC64__) || defined(_ARCH_PPC64)
    return CpuArchitecture::powerpc_64;
    #else
    return CpuArchitecture::powerpc;
    #endif
 
// RISC-V detection
#elif defined(__riscv)
    #if defined(__riscv_xlen) && (__riscv_xlen == 64)
    return CpuArchitecture::risc_v_64;
    #elif defined(__riscv_xlen) && (__riscv_xlen == 32)
    return CpuArchitecture::risc_v_32;
    #else
    return CpuArchitecture::risc_v_64;  // Default to 64-bit RISC-V
    #endif
 
// SPARC detection
#elif defined(__sparc__) || defined(__sparc)
    #if defined(__sparc64__) || defined(__sparcv9)
    return CpuArchitecture::sparc_64;
    #else
    return CpuArchitecture::sparc;
    #endif
 
#else
    return CpuArchitecture::unknown;
#endif
}
 
// Note: detectByteOrder() moved to endianness.hpp as getByteOrder()
 
constexpr int detectPointerSize() noexcept {
    constexpr auto arch = detectCpuArchitecture();
    switch (arch) {
        case CpuArchitecture::x86_64:
        case CpuArchitecture::arm_v8_64:
        case CpuArchitecture::mips_64:
        case CpuArchitecture::powerpc_64:
        case CpuArchitecture::risc_v_64:
        case CpuArchitecture::sparc_64:
            return 64;
 
        case CpuArchitecture::x86:
        case CpuArchitecture::arm_v6:
        case CpuArchitecture::arm_v7:
        case CpuArchitecture::arm_v8_32:
        case CpuArchitecture::mips:
        case CpuArchitecture::powerpc:
        case CpuArchitecture::risc_v_32:
        case CpuArchitecture::sparc:
            return 32;
 
        default:
            return sizeof(void*) * 8;  // Fallback to actual pointer size
    }
}
 
constexpr size_t detectCacheLineSize() noexcept {
    constexpr auto arch = detectCpuArchitecture();
    switch (arch) {
        case CpuArchitecture::x86:
        case CpuArchitecture::x86_64:
            return 64;  // Intel/AMD typical cache line size
 
        case CpuArchitecture::arm_v6:
        case CpuArchitecture::arm_v7:
            return 32;  // Older ARM cores
 
        case CpuArchitecture::arm_v8_32:
        case CpuArchitecture::arm_v8_64:
            return 64;  // Modern ARM cores
 
        case CpuArchitecture::powerpc:
        case CpuArchitecture::powerpc_64:
            return 128;  // PowerPC typical cache line size
 
        case CpuArchitecture::mips:
        case CpuArchitecture::mips_64:
        case CpuArchitecture::risc_v_32:
        case CpuArchitecture::risc_v_64:
        case CpuArchitecture::sparc:
        case CpuArchitecture::sparc_64:
            return 64;  // Common default
 
        default:
            return 64;  // Safe default for unknown architectures
    }
}
 
constexpr const char* getArchitectureName() noexcept {
    constexpr auto arch = detectCpuArchitecture();
    switch (arch) {
        case CpuArchitecture::x86:
            return "x86";
        case CpuArchitecture::x86_64:
            return "x86_64";
        case CpuArchitecture::arm_v6:
            return "ARM v6";
        case CpuArchitecture::arm_v7:
            return "ARM v7";
        case CpuArchitecture::arm_v8_32:
            return "ARM v8 (32-bit)";
        case CpuArchitecture::arm_v8_64:
            return "ARM v8 (64-bit)";
        case CpuArchitecture::mips:
            return "MIPS";
        case CpuArchitecture::mips_64:
            return "MIPS64";
        case CpuArchitecture::powerpc:
            return "PowerPC";
        case CpuArchitecture::powerpc_64:
            return "PowerPC64";
        case CpuArchitecture::risc_v_32:
            return "RISC-V 32";
        case CpuArchitecture::risc_v_64:
            return "RISC-V 64";
        case CpuArchitecture::sparc:
            return "SPARC";
        case CpuArchitecture::sparc_64:
            return "SPARC64";
        default:
            return "Unknown";
    }
}
 
}  // namespace detail
 
constexpr CpuArchitecture getCpuArchitecture() noexcept {
    return detail::detectCpuArchitecture();
}
 
// Note: getByteOrder() is provided by endianness.hpp
 
constexpr ArchitectureInfo getArchitectureInfo() noexcept {
    return ArchitectureInfo{detail::detectCpuArchitecture(),
                            getByteOrder(),  // Use getByteOrder() from endianness.hpp
                            detail::detectPointerSize(),
                            detail::detectCacheLineSize(),
                            detail::getArchitectureName()};
}
 
constexpr int getPointerSize() noexcept {
    return detail::detectPointerSize();
}
 
constexpr bool hasSimdSupport() noexcept {
    constexpr auto arch = getCpuArchitecture();
    return arch == CpuArchitecture::x86 || arch == CpuArchitecture::x86_64 ||
           arch == CpuArchitecture::arm_v7 || arch == CpuArchitecture::arm_v8_32 ||
           arch == CpuArchitecture::arm_v8_64;
}
 
constexpr bool hasVectorInstructions() noexcept {
    // Vector instructions include SIMD and more advanced vector processing
    constexpr auto arch = getCpuArchitecture();
    return arch == CpuArchitecture::x86_64 ||     // SSE/AVX
           arch == CpuArchitecture::arm_v8_64 ||  // NEON/SVE
           arch == CpuArchitecture::risc_v_64;    // RISC-V Vector Extension
}
 
constexpr bool supportsCacheLineAlignment() noexcept {
    // Most modern architectures benefit from cache line alignment
    constexpr auto arch = getCpuArchitecture();
    return arch != CpuArchitecture::unknown;
}
 
constexpr bool is64BitArchitecture() noexcept {
    return getPointerSize() == 64;
}
 
constexpr bool is32BitArchitecture() noexcept {
    return getPointerSize() == 32;
}
 
}  // namespace platform
}  // namespace trlc
 
// Preprocessor-only architecture detection (for use in #if directives)
#if defined(__x86_64__) || defined(__x86_64) || defined(__amd64__) || defined(__amd64) || \
    defined(_M_X64)
    #define TRLC_ARCH_X86_64_PP 1
    #define TRLC_ARCH_64BIT_PP 1
    #define TRLC_ARCH_X86_64 1
    #define TRLC_ARCH_64BIT 1
#else
    #define TRLC_ARCH_X86_64_PP 0
    #define TRLC_ARCH_X86_64 0
#endif
 
#if defined(__aarch64__) || defined(_M_ARM64)
    #define TRLC_ARCH_ARM64_PP 1
    #define TRLC_ARCH_64BIT_PP 1
    #define TRLC_ARCH_ARM64 1
    #define TRLC_ARCH_64BIT 1
#else
    #define TRLC_ARCH_ARM64_PP 0
    #define TRLC_ARCH_ARM64 0
#endif
 
#if defined(__i386__) || defined(__i386) || defined(_M_IX86)
    #define TRLC_ARCH_X86_PP 1
    #define TRLC_ARCH_32BIT_PP 1
    #define TRLC_ARCH_X86 1
    #define TRLC_ARCH_32BIT 1
#else
    #define TRLC_ARCH_X86_PP 0
    #define TRLC_ARCH_X86 0
#endif
 
#if defined(__arm__) || defined(_M_ARM)
    #define TRLC_ARCH_ARM_PP 1
    #define TRLC_ARCH_32BIT_PP 1
    #define TRLC_ARCH_ARM 1
    #define TRLC_ARCH_32BIT 1
#else
    #define TRLC_ARCH_ARM_PP 0
    #define TRLC_ARCH_ARM 0
#endif
 
// Additional architecture family macros
#if defined(__mips__) || defined(__mips) || defined(__MIPS__)
    #define TRLC_ARCH_MIPS 1
#else
    #define TRLC_ARCH_MIPS 0
#endif
 
#if defined(__powerpc__) || defined(__powerpc) || defined(__ppc__) || defined(__ppc) || \
    defined(_M_PPC)
    #define TRLC_ARCH_POWERPC 1
#else
    #define TRLC_ARCH_POWERPC 0
#endif
 
#if defined(__riscv)
    #define TRLC_ARCH_RISCV 1
#else
    #define TRLC_ARCH_RISCV 0
#endif
 
#if defined(__sparc__) || defined(__sparc)
    #define TRLC_ARCH_SPARC 1
#else
    #define TRLC_ARCH_SPARC 0
#endif
 
// Ensure we have consistent bit width detection
#ifndef TRLC_ARCH_64BIT_PP
    #if defined(__LP64__) || defined(_WIN64) || \
        (defined(__SIZEOF_POINTER__) && __SIZEOF_POINTER__ == 8)
        #define TRLC_ARCH_64BIT_PP 1
        #define TRLC_ARCH_32BIT_PP 0
        #define TRLC_ARCH_64BIT 1
        #define TRLC_ARCH_32BIT 0
    #else
        #define TRLC_ARCH_64BIT_PP 0
        #define TRLC_ARCH_32BIT_PP 1
        #define TRLC_ARCH_64BIT 0
        #define TRLC_ARCH_32BIT 1
    #endif
#endif
 
#ifndef TRLC_ARCH_32BIT_PP
    #define TRLC_ARCH_32BIT_PP (!TRLC_ARCH_64BIT_PP)
    #define TRLC_ARCH_32BIT (!TRLC_ARCH_64BIT)
#endif
 
// Byte order macros (preprocessor compatible)
#if defined(__BYTE_ORDER__)
    #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
        #define TRLC_LITTLE_ENDIAN 1
        #define TRLC_BIG_ENDIAN 0
    #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
        #define TRLC_LITTLE_ENDIAN 0
        #define TRLC_BIG_ENDIAN 1
    #else
        #define TRLC_LITTLE_ENDIAN 0
        #define TRLC_BIG_ENDIAN 0
    #endif
#elif defined(__LITTLE_ENDIAN__) || defined(__ARMEL__)
    #define TRLC_LITTLE_ENDIAN 1
    #define TRLC_BIG_ENDIAN 0
#elif defined(__BIG_ENDIAN__) || defined(__ARMEB__)
    #define TRLC_LITTLE_ENDIAN 0
    #define TRLC_BIG_ENDIAN 1
#else
   // Architecture-based endianness detection
    #if TRLC_ARCH_X86 || TRLC_ARCH_X86_64 || TRLC_ARCH_ARM || TRLC_ARCH_ARM64 || TRLC_ARCH_RISCV
        #define TRLC_LITTLE_ENDIAN 1
        #define TRLC_BIG_ENDIAN 0
    #elif TRLC_ARCH_SPARC || TRLC_ARCH_MIPS || TRLC_ARCH_POWERPC
        #define TRLC_LITTLE_ENDIAN 0
        #define TRLC_BIG_ENDIAN 1
    #else
        #define TRLC_LITTLE_ENDIAN 1  // Default to little endian
        #define TRLC_BIG_ENDIAN 0
    #endif
#endif
 
// SIMD and vector capability macros (preprocessor compatible)
#if TRLC_ARCH_X86 || TRLC_ARCH_X86_64 || TRLC_ARCH_ARM || TRLC_ARCH_ARM64
    #define TRLC_HAS_SIMD 1
#else
    #define TRLC_HAS_SIMD 0
#endif
 
#if TRLC_ARCH_X86_64 || TRLC_ARCH_ARM64 || TRLC_ARCH_RISCV
    #define TRLC_HAS_VECTOR 1
#else
    #define TRLC_HAS_VECTOR 0
#endif