Cache-aligned

Checks if cache line alignment is supported/beneficial Determines whether cache line alignment provides performance benefits on the target architecture. Most modern architectures benefit from proper cache line alignment to avoid false sharing and optimize memory bandwidth.

Cache Line Alignment Benefits

• False Sharing Avoidance: Prevent cache line ping-ponging between cores
• Memory Bandwidth: Optimize cache utilization and prefetching
• Atomic Operations: Improve performance of concurrent data structures

Cache Line Sizes

• x86/x64: Typically 64 bytes
• ARM: 32-64 bytes depending on implementation
• PowerPC: Often 128 bytes
• Other architectures: Variable, typically 32-128 bytes

Returns

true if cache line alignment provides performance benefits

Note

This function is constexpr and evaluates at compile time

See also

ArchitectureInfo::cache_line_size for actual cache line size

getArchitectureInfo() for comprehensive cache information

data structure

if constexpr (trlc::platform::supportsCacheLineAlignment()) {
    constexpr auto info = trlc::platform::getArchitectureInfo();
 
    // Align to cache line boundary
    alignas(info.cache_line_size) struct {
        std::atomic<int> counter;
        char padding[info.cache_line_size - sizeof(std::atomic<int>)];
    } cache_aligned_counter;
}

Since

1.0.0