TRLC Platform Library  1.0.0
Header-only C++ library for compile-time platform detection and abstraction
Static Public Member Functions | Public Attributes | List of all members
trlc::platform::ArchitectureInfo Struct Reference

#include <trlc/platform/architecture.hpp>

Static Public Member Functions

static bool is64Bit () const
 Checks if the architecture is 64-bit. More...
 
static bool is32Bit () const
 Checks if the architecture is 32-bit. More...
 
static bool isLittleEndian () const
 Checks if the architecture uses little-endian byte order. More...
 
static bool supportsUnalignedAccess () const
 Checks if the architecture supports unaligned memory access. More...
 
static bool hasSimdSupport () const
 Checks if the architecture supports SIMD instructions. More...
 
static bool isARM () const
 Checks if the architecture is ARM-based. More...
 
static bool isX86 () const
 Checks if the architecture is x86-based. More...
 

Public Attributes

CpuArchitecture architecture
 Detected CPU architecture type. More...
 
ByteOrder byte_order
 Detected byte order (endianness) More...
 
int pointer_size_bits
 Pointer size in bits (32 or 64) More...
 
size_t cache_line_size
 Typical cache line size in bytes. More...
 
const char * arch_name
 Human-readable architecture name. More...
 

Detailed Description

Definition at line 165 of file architecture.hpp.

Member Function Documentation

◆ hasSimdSupport()

static bool trlc::platform::ArchitectureInfo::hasSimdSupport ( ) const
inlinestatic

Checks if the architecture supports SIMD instructions.

Determines whether the target architecture has Single Instruction, Multiple Data (SIMD) capabilities for parallel processing. This enables vectorized algorithms and optimizations.

SIMD Instruction Sets by Architecture

  • x86: MMX, SSE family
  • x86_64: SSE, AVX family
  • ARM v7+: NEON
  • ARM v8: Advanced NEON, SVE (on some implementations)
Returns
true if SIMD instruction support is available
Note
This function is constexpr and evaluates at compile time
See also
hasVectorInstructions() for advanced vector processing capabilities
features.hpp for runtime SIMD feature detection
Since
1.0.0

Definition at line 265 of file architecture.hpp.

◆ is32Bit()

static bool trlc::platform::ArchitectureInfo::is32Bit ( ) const
inlinestatic

Checks if the architecture is 32-bit.

Determines whether the target architecture uses 32-bit pointers and address space. This is important for embedded systems and legacy platform compatibility.

Returns
true if architecture uses 32-bit pointers, false otherwise
Note
This function is constexpr and evaluates at compile time
See also
is64Bit() for the complementary check
getPointerSize() for the actual pointer size in bits
Since
1.0.0

Definition at line 200 of file architecture.hpp.

◆ is64Bit()

static bool trlc::platform::ArchitectureInfo::is64Bit ( ) const
inlinestatic

Checks if the architecture is 64-bit.

Determines whether the target architecture uses 64-bit pointers and address space. This is useful for selecting architecture-specific optimizations and determining memory layout constraints.

Returns
true if architecture uses 64-bit pointers, false otherwise
Note
This function is constexpr and evaluates at compile time
See also
is32Bit() for the complementary check
getPointerSize() for the actual pointer size in bits
Since
1.0.0

Definition at line 185 of file architecture.hpp.

◆ isARM()

static bool trlc::platform::ArchitectureInfo::isARM ( ) const
inlinestatic

Checks if the architecture is ARM-based.

Determines whether the target architecture belongs to the ARM family. This is useful for ARM-specific optimizations and feature detection.

ARM Architecture Variants Detected

  • ARMv6: Older embedded systems (e.g., original Raspberry Pi)
  • ARMv7: Common in mobile devices and embedded systems
  • ARMv8 (32-bit): Modern ARM in 32-bit execution mode
  • ARMv8 (64-bit): Modern ARM in 64-bit execution mode (ARM64/AArch64)
Returns
true if architecture is any ARM variant
Note
This function is constexpr and evaluates at compile time
See also
isX86() for x86 family detection
Since
1.0.0

Definition at line 289 of file architecture.hpp.

◆ isLittleEndian()

static bool trlc::platform::ArchitectureInfo::isLittleEndian ( ) const
inlinestatic

Checks if the architecture uses little-endian byte order.

Determines the byte ordering used by the target architecture. Little-endian systems store the least significant byte first, which is common on x86/x64 and most ARM systems.

Returns
true if architecture uses little-endian byte order, false otherwise
Note
This function is constexpr and evaluates at compile time
See also
endianness.hpp for comprehensive endianness utilities
Since
1.0.0
Examples
/home/tranglc/sources/trlc-platform/include/trlc/platform/core.hpp.

Definition at line 214 of file architecture.hpp.

◆ isX86()

static bool trlc::platform::ArchitectureInfo::isX86 ( ) const
inlinestatic

Checks if the architecture is x86-based.

Determines whether the target architecture belongs to the Intel x86 family. This includes both 32-bit x86 and 64-bit x86_64 (AMD64) architectures.

x86 Architecture Variants Detected

  • x86: 32-bit Intel/AMD processors (legacy)
  • x86_64: 64-bit Intel/AMD processors (modern desktop/server)
Returns
true if architecture is x86 or x86_64
Note
This function is constexpr and evaluates at compile time
See also
isARM() for ARM family detection
Since
1.0.0

Definition at line 310 of file architecture.hpp.

◆ supportsUnalignedAccess()

static bool trlc::platform::ArchitectureInfo::supportsUnalignedAccess ( ) const
inlinestatic

Checks if the architecture supports unaligned memory access.

Determines whether the target architecture can efficiently handle memory accesses that are not aligned to natural boundaries. This affects memory access patterns and data structure layout decisions.

Architectures with Efficient Unaligned Access

  • x86/x64: Hardware support for unaligned access
  • ARMv7+: Modern ARM cores handle unaligned access efficiently

Architectures Requiring Alignment

  • ARMv6 and earlier: May trap or perform poorly on unaligned access
  • Some RISC architectures: May require alignment for optimal performance
Returns
true if unaligned memory access is efficiently supported
Note
This function is constexpr and evaluates at compile time
See also
cache_line_size for optimal alignment boundaries
Since
1.0.0
Examples
/home/tranglc/sources/trlc-platform/include/trlc/platform/core.hpp.

Definition at line 238 of file architecture.hpp.

Member Data Documentation

◆ arch_name

const char* trlc::platform::ArchitectureInfo::arch_name

Human-readable architecture name.

Examples
/home/tranglc/sources/trlc-platform/include/trlc/platform/core.hpp.

Definition at line 170 of file architecture.hpp.

◆ architecture

CpuArchitecture trlc::platform::ArchitectureInfo::architecture

Detected CPU architecture type.

Definition at line 166 of file architecture.hpp.

◆ byte_order

ByteOrder trlc::platform::ArchitectureInfo::byte_order

Detected byte order (endianness)

Examples
/home/tranglc/sources/trlc-platform/include/trlc/platform/core.hpp.

Definition at line 167 of file architecture.hpp.

◆ cache_line_size

size_t trlc::platform::ArchitectureInfo::cache_line_size

Typical cache line size in bytes.

Examples
/home/tranglc/sources/trlc-platform/include/trlc/platform/core.hpp.

Definition at line 169 of file architecture.hpp.

◆ pointer_size_bits

int trlc::platform::ArchitectureInfo::pointer_size_bits

Pointer size in bits (32 or 64)

Examples
/home/tranglc/sources/trlc-platform/include/trlc/platform/core.hpp.

Definition at line 168 of file architecture.hpp.

The documentation for this struct was generated from the following file: