architecture.hpp File Reference

CPU architecture and byte order detection for trlc-platform. More...

#include <cstddef>
#include "endianness.hpp"

Go to the source code of this file.

Classes
struct	trlc::platform::ArchitectureInfo

Namespaces
	trlc
	trlc::platform
	trlc::platform::detail

Macros
#define	TRLC_ARCH_X86_64_PP   0
#define	TRLC_ARCH_X86_64   0
#define	TRLC_ARCH_ARM64_PP   0
#define	TRLC_ARCH_ARM64   0
#define	TRLC_ARCH_X86_PP   0
#define	TRLC_ARCH_X86   0
#define	TRLC_ARCH_ARM_PP   0
#define	TRLC_ARCH_ARM   0
#define	TRLC_ARCH_MIPS   0
#define	TRLC_ARCH_POWERPC   0
#define	TRLC_ARCH_RISCV   0
#define	TRLC_ARCH_SPARC   0
#define	TRLC_ARCH_64BIT_PP   0
#define	TRLC_ARCH_32BIT_PP   1
#define	TRLC_ARCH_64BIT   0
#define	TRLC_ARCH_32BIT   1
#define	TRLC_LITTLE_ENDIAN   1
#define	TRLC_BIG_ENDIAN   0
#define	TRLC_HAS_SIMD   0
#define	TRLC_HAS_VECTOR   0

Enumerations
enum class	trlc::platform::CpuArchitecture : int {   trlc::platform::unknown = 0 , trlc::platform::x86 , trlc::platform::x86_64 , trlc::platform::arm_v6 ,   trlc::platform::arm_v7 , trlc::platform::arm_v8_32 , trlc::platform::arm_v8_64 , trlc::platform::mips ,   trlc::platform::mips_64 , trlc::platform::powerpc , trlc::platform::powerpc_64 , trlc::platform::risc_v_32 ,   trlc::platform::risc_v_64 , trlc::platform::sparc , trlc::platform::sparc_64 }
	CPU architecture enumeration. More...

Functions
static CpuArchitecture	trlc::platform::detail::detectCpuArchitecture ()
	Detects CPU architecture using compiler predefined macros. More...
static int	trlc::platform::detail::detectPointerSize ()
	Determines pointer size based on architecture. More...
static size_t	trlc::platform::detail::detectCacheLineSize ()
	Determines typical cache line size for architecture. More...
static const char *	trlc::platform::detail::getArchitectureName ()
	Gets human-readable architecture name. More...
static CpuArchitecture	trlc::platform::getCpuArchitecture ()
static ArchitectureInfo	trlc::platform::getArchitectureInfo ()
static int	trlc::platform::getPointerSize ()
static bool	trlc::platform::hasSimdSupport ()
static bool	trlc::platform::hasVectorInstructions ()
static bool	trlc::platform::supportsCacheLineAlignment ()
static bool	trlc::platform::is64BitArchitecture ()
static bool	trlc::platform::is32BitArchitecture ()

Detailed Description

CPU architecture and byte order detection for trlc-platform.

This header provides comprehensive compile-time detection of CPU architecture, byte order, and architecture-specific capabilities. All functions are constexpr and evaluate at compile time for zero runtime overhead.

Features

• Compile-time CPU architecture detection (x86, ARM, MIPS, PowerPC, RISC-V, SPARC)
• Pointer size detection (32-bit vs 64-bit)
• Cache line size estimation for optimization
• SIMD and vector instruction capability detection
• Architecture family classification (ARM vs x86 vs others)
• Preprocessor macros for conditional compilation

Supported Architectures

• x86 Family: x86 (32-bit), x86_64 (64-bit)
• ARM Family: ARMv6, ARMv7, ARMv8 (32/64-bit)
• MIPS Family: MIPS (32/64-bit)
• PowerPC Family: PowerPC (32/64-bit)
• RISC-V Family: RISC-V (32/64-bit)
• SPARC Family: SPARC (32/64-bit)

Performance Characteristics

• Zero Runtime Overhead: All detection occurs at compile time
• Header-Only: No linking required
• Thread-Safe: Purely compile-time evaluation
• Optimizable: Enables compiler optimizations through constexpr

Thread Safety

All functions in this header are thread-safe as they perform only compile-time evaluation and access no mutable state.

Definition in file architecture.hpp.

Macro Definition Documentation

TRLC_ARCH_32BIT

#define TRLC_ARCH_32BIT   1

Definition at line 936 of file architecture.hpp.

TRLC_ARCH_32BIT_PP

#define TRLC_ARCH_32BIT_PP   1

Definition at line 934 of file architecture.hpp.

TRLC_ARCH_64BIT

#define TRLC_ARCH_64BIT   0

Definition at line 935 of file architecture.hpp.

TRLC_ARCH_64BIT_PP

#define TRLC_ARCH_64BIT_PP   0

Definition at line 933 of file architecture.hpp.

TRLC_ARCH_ARM

#define TRLC_ARCH_ARM   0

Definition at line 895 of file architecture.hpp.

TRLC_ARCH_ARM64

#define TRLC_ARCH_ARM64   0

Definition at line 875 of file architecture.hpp.

TRLC_ARCH_ARM64_PP

#define TRLC_ARCH_ARM64_PP   0

Definition at line 874 of file architecture.hpp.

TRLC_ARCH_ARM_PP

#define TRLC_ARCH_ARM_PP   0

Definition at line 894 of file architecture.hpp.

TRLC_ARCH_MIPS

#define TRLC_ARCH_MIPS   0

Definition at line 902 of file architecture.hpp.

TRLC_ARCH_POWERPC

#define TRLC_ARCH_POWERPC   0

Definition at line 909 of file architecture.hpp.

TRLC_ARCH_RISCV

#define TRLC_ARCH_RISCV   0

Definition at line 915 of file architecture.hpp.

TRLC_ARCH_SPARC

#define TRLC_ARCH_SPARC   0

Definition at line 921 of file architecture.hpp.

TRLC_ARCH_X86

#define TRLC_ARCH_X86   0

Definition at line 885 of file architecture.hpp.

TRLC_ARCH_X86_64

#define TRLC_ARCH_X86_64   0

Definition at line 865 of file architecture.hpp.

TRLC_ARCH_X86_64_PP

#define TRLC_ARCH_X86_64_PP   0

Definition at line 864 of file architecture.hpp.

TRLC_ARCH_X86_PP

#define TRLC_ARCH_X86_PP   0

Definition at line 884 of file architecture.hpp.

TRLC_BIG_ENDIAN

#define TRLC_BIG_ENDIAN   0

Definition at line 973 of file architecture.hpp.

TRLC_HAS_SIMD

#define TRLC_HAS_SIMD   0

Definition at line 981 of file architecture.hpp.

TRLC_HAS_VECTOR

#define TRLC_HAS_VECTOR   0

Definition at line 987 of file architecture.hpp.

TRLC_LITTLE_ENDIAN

#define TRLC_LITTLE_ENDIAN   1

Definition at line 972 of file architecture.hpp.